參數(shù)資料
型號(hào): MPC8545EVUANJ
廠商: Freescale Semiconductor
文件頁數(shù): 76/151頁
文件大小: 0K
描述: IC MPU PWRQUICC III 783-FCCBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 800MHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
30
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC)
Figure 7. FIFO Receive AC Timing Diagram
8.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2.1
GMII Transmit AC Timing Specifications
This table provides the GMII transmit AC timing specifications.
Table 26. GMII Transmit AC Timing Specifications
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
GMII data TXD[7:0], TX_ER, TX_EN setup time
tGTKHDV
2.5
ns
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
tGTKHDX
0.5
5.0
ns
GTX_CLK data clock rise time (20%–80%)
tGTXR
2
——
1.0
ns
GTX_CLK data clock fall time (80%–20%)
tGTXF
2
——
1.0
ns
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing
(GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
tFIR
tFIRH
tFIRF
tFIRR
RX_CLK
RXD[7:0]
RX_DV
RX_ER
Valid Data
tFIRDV
tFIRDX
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