參數(shù)資料
型號(hào): MPC8544VTARJ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件頁(yè)數(shù): 45/112頁(yè)
文件大?。?/td> 1294K
代理商: MPC8544VTARJ
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
38
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 19 shows the TBI transmit AC timing diagram.
Figure 19. TBI Transmit AC Timing Diagram
8.4.4.2
TBI Receive AC Timing Specifications
Table 36 provides the TBI receive AC timing specifications.
GTX_CLK rise (20%–80%)
tTTXR
——
1.0
ns
GTX_CLK fall time (80%–20%)
tTTXF
——
1.0
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI
transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid
state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going
high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript
of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. Data valid tTTKHDV to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time –
Max delay).
Table 36. TBI Receive AC Timing Specifications
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
PMA_RX_CLK[0:1] clock period
tTRX
16.0
ns
PMA_RX_CLK[0:1] skew
tSKTRX
7.5
8.5
ns
PMA_RX_CLK[0:1] duty cycle
tTRXH/tTRX
40
60
%
RCG[9:0] setup time to rising PMA_RX_CLK
tTRDVKH
2.5
ns
PMA_RX_CLK to RCG[9:0] hold time
tTRDXKH
1.5
ns
PMA_RX_CLK[0:1] clock rise time (20%-80%)
tTRXR
0.7
2.4
ns
Table 35. TBI Transmit AC Timing Specifications (continued)
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
GTX_CLK
TCG[9:0]
tTTX
tTTXH
tTTXR
tTTXF
tTTKHDV
tTTKHDX
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