參數(shù)資料
型號： MPC8544AVTARJ
廠商： Freescale Semiconductor
文件頁數(shù)： 80/117頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCBGA
產(chǎn)品培訓(xùn)模塊： MPC8544E PowerQUICC™ III
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.067GHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
配用： MPC8544DS-ND - BOARD DEVELOPMENT SYSTEM 8544
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
65
High-Speed Serial Interfaces (HSSI)
Figure 44. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)
is 1000 mV p-p.
16.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for PCI Express1, PCI Express2. SD2_REF_CLK, and SD2_REF_CLK for the PCI
Express3 or SGMII interface, respectively. The following sections describe the SerDes reference clock
requirements and some application information.
16.2.1
SerDes Reference Clock Receiver Characteristics
Figure 45 shows a receiver reference diagram of the SerDes reference clocks.
The supply voltage requirements for XVDD_SRDS2 are specified in Table 1 and Table 2.
SerDes reference clock receiver reference circuit structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in Figure 45. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
50-
Ωtermination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SDn_TX or
SDn_RX
SDn_TX or
SDn_RX
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Vcm = (A + B) / 2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8544AVTARJA 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC PQ38K 8544 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8544COMEDEV 功能描述:開發(fā)板和工具包 - 其他處理器 EXPRESS KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8544CVTALF 功能描述:微處理器 - MPU PQ38K 8544 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8544CVTALFA 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC PQ38K 8544 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8544CVTANG 功能描述:微處理器 - MPU PQ38K 8544 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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