參數(shù)資料
型號(hào)： MPC8541EPXAJDX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù)： 21/84頁(yè)
文件大?。?/td> 1241K
代理商： MPC8541EPXAJDX
MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
28
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
8.2.5
RGMII and RTBI AC Timing Specifications
Table 26 presents the RGMII and RTBI AC timing specifications.
Table 26. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
5
–500
0
500
ps
Data to clock input skew (at receiver) 2
tSKRGT
1.0
—
2.8
ns
Clock cycle duration 3
tRGT
6
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T 4
tRGTH/tRGT
6
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3
tRGTH/tRGT
6
40
50
60
%
Rise and fall times
tRGTR
6,7
, tRGTF
6,7
—
0.75
ns
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. The RGMII specification requires that PC board designer add 1.5 ns or greater in trace delay to the RX_CLK in order to meet
this specification. However, as stated above, this device will function with only 1.0 ns of delay.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Guaranteed by characterization.
6. Guaranteed by design.
7. Signal timings are measured at 0.5 V and 2.0 V voltage levels.
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