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參數(shù)資料
| 型號： | MPC8540VT667LB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | ICMPU 32BIT 667MHZ PPC 783FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 667MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
| 配用： | MPC8540ADS-BGA-ND - BOARD APPLICATION DEV 8540 CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540 |
MPC8540 PowerQUICC III Integrated Host Processor Product Brief, Rev. 0.1
12
Freescale Semiconductor
MPC8540 Architecture Overview
The L2 status array maintains status bits for each line to determine the status of the line. Different combinations of
these bits result in different L2 states. Note that because the cache is always write-through, there is no modified state.
The status bits include the following:
V—Valid
IL—Instruction locked
DL—Data locked
All accesses to the L2 memory are fully pipelined so back-to-back loads and stores can have single-cycle throughput.
The cache can be configured to allocate instructions-only, data-only, or both. It can also be configured to allocate
global I/O writes that correspond to a programmable address window or that use a special transaction type (stashing).
In this way, DMA engines or I/O devices can force data into the cache.
Line locks can be set in a variety of ways. The Book E architecture defines instructions that explicitly set and clear
locks in the L2. These instructions are supported by the core complex and the L2 controller. In addition, the L2
controller can be configured to lock all lines that fall into either of two specified address ranges when the line is
allocated. Finally, the entire cache can be locked by writing to a configuration register in the L2 cache controller.
The status array tracks line locks as either instruction locks or data locks for each line, and the status array supports
flash clearing of all instruction locks or data locks separately by writes to configuration registers in the L2 controller.
3.3 e500 Coherency Module (ECM)
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus between
the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable memory. It also
provides a flexible switch-type structure for core and I/O-initiated transactions to be routed or dispatched to target
modules on the device.
3.4 DDR SDRAM Controller
The MPC8540 supports DDR-I SDRAM that operates at up to 166 MHz (333-MHz data rate). The memory interface
controls main memory accesses and provides for a maximum of 3.5 Gbytes of main memory. The memory controller
can be configured to support the various memory sizes through software initialization of on-chip configuration
registers.
The MPC8540 supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs or
directly-attached memory devices. Fifteen multiplexed address signals provide for device densities of 64 Mbits,
128 Mbits, 256 Mbits, and 512 Mbits, and 1 Gbit. Four chip select signals support up to four banks of memory. The
MPC8540 supports bank sizes from 64 Mbytes to 1 Gbyte. Nine-column address strobes (MDM[0:8]) are used to
provide byte selection for memory bank writes.
The MPC8540 can be configured to retain the currently active SDRAM page for pipelined burst accesses. Page
mode support of up to 16 simultaneously open pages can dramatically reduce access latencies for page hits.
Depending on the memory system design and timing parameters, using page mode can save 3 to 4 clock cycles from
subsequent burst accesses that hit in an active page.
The MPC8540 supports ECC for system memory. Using ECC, the MPC8540 detects and corrects all single-bit
errors and detects all double-bit errors and all errors within a nibble.
The MPC8540 can invoke a level of system power management by asserting the MCKE SDRAM signal on-the-fly
to put the memory into a low-power sleep mode.
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參數(shù)描述 |
|---|---|
| MPC8540VT667LC | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540VT833LB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540VT833LC | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540VTAQFB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8540VTAQFC | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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