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參數(shù)資料
| 型號： | MPC8536EBVTAVLA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 20/126頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU PWRQUICC III 1500MHZ 783PBGA |
| 產(chǎn)品培訓(xùn)模塊： | MPC8536E QUICC III Processor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.5GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
| 其它名稱： | MPC8536EBVTAVL MPC8536EBVTAVL-ND |
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MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Hardware Design Considerations
Freescale Semiconductor
116
These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to
minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD,
BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types
and quantity of bulk capacitors.
3.5
SerDes Block Power Supply Decoupling Recommendations
he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnVDD and XnVDD) to ensure low jitter on
transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to
power and ground should be done with multiple vias to further reduce inductance.
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the chip. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
chip as close to the supply and ground connections as possible.
Second, there should be a 1-F ceramic chip capacitor from each SerDes supply (SnVDD and XnVDD) to the board
ground plane on each side of the chip. This should be done for all SerDes supplies.
Third, between the chip and any SerDes voltage regulator there should be a 10-F, low equivalent series resistance
(ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT tantalum chip capacitor. This should be done for all
SerDes supplies.
3.6
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs should be tied to VDD,TVDD, BVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be
connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all
external VDD,TVDD, BVDD, OVDD, GVDD, and LVDD and GND pins of the chip.
3.7
Pull-Up and Pull-Down Resistor Requirements
The chip requires weak pull-up resistors (2–10 k
Ω is recommended) on open drain type pins including I2C pins and MPIC
interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC1_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The UART_SOUT[0:1] and TEST_SEL pins must be set to a
proper state during POR configuration. Please refer to the pinlist table (see Table 62) of the individual chip for more details.
See the PCI 2.2 specification for all pull-ups required for PCI.
3.8
Output Buffer DC Impedance
The chip drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended
driver type (open drain for I
2C).
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