參數(shù)資料
型號： MPC8536CVTAVLA
廠商： Freescale Semiconductor
文件頁數(shù)： 124/126頁
文件大?。?/td> 0K
描述： MPU PWRQUICC III 1500MHZ 783PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
其它名稱： MPC8536CVTAVL
MPC8536CVTAVL-ND
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
97
This figure shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL
driver’s DC levels (both common mode voltages and output swing) are incompatible with chip’s SerDes reference clock input’s
DC requirement, AC-coupling has to be used. This figure assumes that the LVPECL clock driver’s output impedance is 50
Ω.
R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140
Ω to 240Ω depending on
clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-
Ω termination resistor to
attenuate the LVPECL output’s differential peak level such that it meets the chip’s SerDes reference clock’s differential input
amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak
is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which
requires R2 = 25
Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with
a particular clock driver chip.
Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC
levels of the clock driver are compatible with chip’s SerDes reference clock input’s DC requirement.
Figure 65. Single-Ended Connection (Reference Only)
50
Ω
50
Ω
SDn_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK
Driver Chip
R2
R1
10nF
10 nF
50
Ω
50
Ω
SDn_REF_CLK
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended
CLK Driver Chip
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
50
Ω
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MPC8536E-ANDROID 功能描述:開發(fā)板和工具包 - 其他處理器 COMEXPRESS BASED RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
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