參數(shù)資料
型號(hào)： MPC8536CVTAVLA
廠商： Freescale Semiconductor
文件頁數(shù)： 11/126頁
文件大?。?/td> 0K
描述： MPU PWRQUICC III 1500MHZ 783PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
其它名稱： MPC8536CVTAVL
MPC8536CVTAVL-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
108
2.23.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency
of the CCB is set using the following reset signals, as shown in the following table:
SYSCLK input signal
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values.
2.23.3
e500 Core PLL Ratio
This table describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined
by the binary value of LBCTL, LALE and LGPL2 at power up, as shown in this table.
2.23.4
DDR/DDRCLK PLL Ratio
The DDR memory controller complex can be synchronous with, or asynchronous to, the CCB, depending on configuration.
The following table describes the clock ratio between the DDR memory controller complex and the DDR/DDRCLK PLL
reference clock, DDRCLK, which is not the memory bus clock.
When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default mode of operation
is for the DDR data rate for the DDR controller to be equal to the CCB clock rate in synchronous mode, or the resulting DDR
PLL rate in asynchronous mode.
In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 77 reflects the DDR data rate to DDRCLK ratio,
since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output.
Table 75. CCB Clock Ratio
Binary Value of
LA[28:31] Signals
CCB:SYSCLK Ratio
Binary Value of
LA[28:31] Signals
CCB:SYSCLK Ratio
0000
16:1
1000
8:1
0001
Reserved
1001
9:1
0010
Reserved
1010
10:1
0011
3:1
1011
Reserved
0100
4:1
1100
12:1
0101
5:1
1101
Reserved
0110
6:1
1110
Reserved
0111
Reserved
1111
Reserved
Table 76. e500 Core to CCB Clock Ratio
Binary Value of
LBCTL, LALE,
LGPL2 Signals
e500 core: CCB Clock Ratio
Binary Value of
LBCTL, LALE,
LGPL2 Signals
e500 core: CCB Clock Ratio
000
4:1
100
2:1
001
9:2
101
5:2
010
Reserved
110
3:1
011
3:2
111
7:2
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參數(shù)描述
MPC8536DS 功能描述:微處理器 - MPU MPC8536 Dev Platform RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8536E-ANDROID 功能描述:開發(fā)板和工具包 - 其他處理器 COMEXPRESS BASED RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
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MPC8536EAVTAKGA 功能描述:微處理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8536EAVTANG 功能描述:微處理器 - MPU PQ38S 8536 SQUID RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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