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參數(shù)資料
| 型號： | MPC8535ECVTAQG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 40/126頁 |
| 文件大小： | 0K |
| 描述： | MCU PWRQUICC II 1000MHZ 783-PBGA |
| 標準包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.0GHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Pin Assignments and Reset States
Freescale Semiconductor
20
Notes:
1. All multiplexed signals may be listed only once and may not re-occur.
2. Recommend a weak pull-up resistor (2–10 K
Ω) be placed on this pin to OVDD.
3. This pin must always be pulled-high.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pullup or active driver is needed.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ω pull-up or pull-down
resistors. See Section 22.2, “CCB/SYSCLK PLL Ratio.”
8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-k
Ω
pull-up or pull-down resistors. See the Section 22.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
10.For proper state of these signals during reset, UART_SOUT[1] must be pulled down to GND through a resistor.
UART_SOUT[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down
the value of the net at reset, then a pullup is needed on UART_SOUT[0].
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the VDD_CORE/VDD_PLAT/GND planes internally and may be used by the core power supply to
improve tracking and regulation.
15. These pins have other manufacturing or debug test functions. It’s recommended to add both pull-up resistor pads to OVDD
and pull-down resistor pads to GND on board to support future debug testing when needed.
16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe
state during reset.
17. This pin is only an output in FIFO mode when used as Rx Flow Control.
18. Do not connect.
19.These must be pulled up (100
Ω- 1 kΩ) to OVDD.
20. Independent supplies derived from board VDD.
21. Recommend a pull-up resistor (1 K
Ω) be placed on this pin to OVDD.
22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0], EC_MDC, TSEC1_TXD[3],
TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.
23. This pin requires an external 4.7-k
Ω pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
24. General-Purpose POR configuration of user system.
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
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