參數(shù)資料
型號(hào)： MPC8535EBVTATHA
廠商： Freescale Semiconductor
文件頁數(shù)： 76/126頁
文件大小： 0K
描述： MCU PWRQUICC II 1250MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.25GHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
其它名稱： MPC8535EBVTATH
MPC8535EBVTATH-ND
Electrical Characteristics
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
53
This figure provides the AC test load for eTSEC.
Figure 27. eTSEC AC Test Load
This figure shows the RMII receive AC timing diagram.
Figure 28. RMII Receive AC Timing Diagram
2.9.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of the chip as shown in
Figure 29, where CTX is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential
pair features 50-
Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 68.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be
left floating. The input signals should be terminated based on the guidelines described in Section 3.6, “Connection
Recommendations,” as long as such termination does not violate the desired POR configuration requirement on these pins, if
applicable.
Fall time TSECn_RX_CLK (80%–20%)
tRMRF
1.0
—
2.0
ns
RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge
tRMRDV
4.0
——ns
RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge
tRMRDX
2.0
——ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going
to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
Table 37. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
TSECn_RX_CLK
RXD[1:0]
tRMRDX
tRMR
tRMRH
tRMRR
tRMRF
CRS_DV
RX_ER
tRMRDV
Valid Data
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MPC8535ECVTANG 功能描述:微處理器 - MPU 8535E INDUSTRIAL 800 EXT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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