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參數(shù)資料
| 型號(hào)： | MPC8533EVTARJ |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783 |
| 文件頁(yè)數(shù)： | 80/116頁(yè) |
| 文件大?。?/td> | 1273K |
| 代理商： | MPC8533EVTARJ |
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MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
66
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 46 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8533E SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-
Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
Figure 46. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 47 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
MPC8533E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 47
assumes that the LVPECL clock driver’s output impedance is 50
Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140 to 240
Ω depending on clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-
Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8533E SerDes
reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak).
For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock
input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25
Ω. Please
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVDS CLK Driver Chip
10 nF
MPC8533E
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8533EVTARJA | 功能描述:微處理器 - MPU PQ38K 8533E RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8533VTALF | 功能描述:微處理器 - MPU PQ38K 8533 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8533VTALFA | 功能描述:微處理器 - MPU PQ38K 8533 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8533VTANG | 功能描述:微處理器 - MPU PQ38K 8533 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8533VTANGA | 功能描述:微處理器 - MPU PQ38K 8533 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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