參數(shù)資料
型號: MPC8533EVTALJB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù): 9/116頁
文件大?。?/td> 1277K
代理商: MPC8533EVTALJB
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
106
Freescale Semiconductor
System Design Information
Figure 63. Driver Impedance Measurement
Table 68 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,
nominal OVDD, 90°C.
21.8
Configuration Pin Muxing
The MPC8533E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k
Ω on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 k
Ω. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Table 68. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI
DDR DRAM
Symbol
Unit
RN
43 Target
25 Target
20 Target
Z0
W
RP
43 Target
25 Target
20 Target
Z0
W
Note: Nominal supply voltages. See Table 1.
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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MPC8533VTARFB 32-BIT, 1067 MHz, RISC PROCESSOR, PBGA783
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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