
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
22
Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 4. Timing Diagram for tDDKHMH
Figure 5 shows the DDR SDRAM output timing diagram.
Figure 5. DDR and DDR2 SDRAM Output Timing Diagram
Figure 6 provides the AC test load for the DDR bus.
Figure 6. DDR AC Test Load
MDQS
MCK[n]
tMCK
MDQS
tDDKHMH(max) = 0.6 ns
tDDKHMH(min) = –0.6 ns
ADDR/CMD
tDDKHAS, tDDKHCS
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK
tMCK
tDDKLDX
tDDKHDX
D1
D0
tDDKHAX, tDDKHCX
Write A0
NOOP
tDDKHME
tDDKHMP
tDDKHMH
Output
Z0 = 50 Ω
GVDD/2
RL = 50 Ω