參數(shù)資料
型號(hào)： MPC850ZT33
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 9/12頁(yè)
文件大小： 70K
代理商： MPC850ZT33
6
MPC850/MPC850SE Technical Summary
MOTOROLA
– Segment CPCS_PDU directly from system memory
– CPCS_PDU padding
– CRC32 generation
– Automatic last cell marking (in PTI field of cell header)
– Automatic CS_UU, CPI, and LENGTH insertion in last cell
— AAL5 segmentation and reassembly (SAR) features for reassembly:
– Reassembles CPCS_PDU directly into system memory
– Removes CPCS_PDU padding
– CRC32 checking
– CS_UU, CPI, and LENGTH reporting
– CLP and congestion reporting
– Interrupts per buffer or per message
– Error reporting, including CRC, length mismatch, message abort
— AAL0 features for transmit include the following:
– Transmits user-defined cell from transmit memory buffer
– Automatic HEC generation
– Optional CRC10 insertion
— AAL0 features for receive include the following:
– Copies entire cell into receive memory buffer
– Provides interrupt per cell
– Optional CRC10 checking
Two serial management controllers (SMCs)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division-multiplexed (TDM) channels
One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus
One I2C (interprocessor-integrated circuit) port
— Supports master and slave modes
— Supports multimaster environment
Time slot assigner
— Allows SCCs and SMCs to run in multiplexed and/or nonmultiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, Frame Syncs, clocking
— Allows dynamic changes
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