參數(shù)資料
型號: MPC850ZT33
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA256
封裝: PLASTIC, BGA-256
文件頁數(shù): 5/12頁
文件大?。?/td> 70K
代理商: MPC850ZT33
2
MPC850/MPC850SE Technical Summary
MOTOROLA
Figure 1. MPC850 Microprocessor Block Diagram
1.1 Features
The following list summarizes the main features of the MPC850:
Embedded PowerPC core with 87 MIPS at 66 MHz (using Dhrystone 2.1)
— Single issue, 32-bit version of the embedded PowerPC core (fully compatible with PowerPC
user instruction set architecture definition) with 32 x 32-bit fixed-point registers
— Power consumption lower than 330 mW (typical) at 33 MHz, 2.2-V internal, 3.3-V I/O
boundary with microprocessor core, caches, memory management, and I/O in operation
— Performs branch folding and branch prediction with conditional prefetch, but without
conditional execution
— 2-Kbyte data cache and 1-Kbyte instruction cache
— Instruction and data caches are two-way, set associative, physical address, 4-word line burst,
System Interface Unit
Memory Controller
Bus Interface Unit
System Functions
Real-time Clock
PCMCIA Interface
Bus
Embedded
2-Kbyte
I Cache
MMU
1-Kbyte
D Cache
Data
MMU
Load/Store
Instruction
Bus
Parallel I/O
Baud Rate
Generators
Dual-port
RAM
Interrupt
Controller
Four
Timers
14 Serial
2 Virtual
32-Bit RISC Microcontroller
and Program ROM
USB
SMC2
SPI
SCC3
Timer
Serial Interface
Time Slot Assigner
SMC1
MAC
PowerPC
Core
Instruction
IDMA
Channels
DMA
and
Channels
Unified Bus
Communication
Processor
Module
Peripheral Bus
SCC2
I2C
Parallel
Port Pins/
UTOPIA
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