參數(shù)資料
型號: MPC8379EVRANGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 54/114頁
文件大小: 1337K
代理商: MPC8379EVRANGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
Figure 26 provides the eSDHC clock input timing diagram.
Figure 26. eSDHC Clock Input Timing Diagram
Input hold times: SD_CMD, SD_DAT
x, SD_CD to
SD_CLK
tSFSIXKH
0—
ns
SD_CLK delay within device
tINT_CLK_DLY
1.5
ns
Output valid: SD_CLK to SD_CMD, SD_DAT
x valid
tSFSKHOV
—4
ns
Output hold: SD_CLK to SD_CMD, SD_DAT
x valid
tSFSKHOX
0—
SD card input setup
tISU
5—
ns
SD card input hold
tIH
5—
ns
SD card output valid
tODLY
—14
ns
SD card output hold
tOH
0—
ns
Notes:
1 The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going
to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect
to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is
based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
2 Measured at capacitive load of 40 pF.
3 For reference only, according to the SD card specifications.
4 Average, for reference only.
Table 41. eSDHC AC Timing Specifications for Full-Speed Mode (continued)
At recommended operating conditions OVDD = 3.3 V ± 165 mV.
Parameter
Symbol 1
Min
Max
Unit
Notes
eSDHC
tSFSCKR
External Clock
VM
tSFSCK
tSFSCKF
VM = Midpoint Voltage (OVDD/2)
operational mode
tSFSCKL
tSFSCKH
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