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| 型號(hào)： | MPC8379EVRANGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁(yè)數(shù)： | 24/114頁(yè) |
| 文件大?。?/td> | 1337K |
| 代理商： | MPC8379EVRANGA |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
17
DDR1 and DDR2 SDRAM
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V
Parameter
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
I/O reference voltage
MVREF
0.49
× GVDD
0.51
× GVDD
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.18
V
—
Output leakage current
IOZ
–40
40
μA4
Output high current (VOUT = 1.9 V)
IOH
–15.2
—
mA
—
Output low current (VOUT = 0.38 V)
IOL
15.2
—
mA
—
Note:
1 GV
DD is expected to be within 50 mV of the DRAM GVDD at all times.
2 MV
REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3 V
TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4 Output leakage is measured with all outputs disabled, 0 V
≤ VOUT ≤ GVDD.
5 See AN3665, MPC837xE Design Checklist, for proper DDR termination.
Table 15. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V
Parameter
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
Note:
1 This parameter is sampled. GV
DD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT =GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 16. Current Draw Characteristics for MVREF
Parameter
Symbol
Min
Typ
Max
Unit
Note
Current draw for MVREF
DDR1
DDR2
IMVREF
—
250
150
600
400
Note:
1 The voltage regulator for MV
REF must be able to supply up to the stated maximum current.
2 This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8379EZQAFDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAFFA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAGDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAGFA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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