參數(shù)資料
型號: MPC8379EVRAJF
廠商: Freescale Semiconductor
文件頁數(shù): 97/127頁
文件大?。?/td> 0K
描述: MPU PWRQUICC II 533MHZ 689TEPBGA
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
71
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i
or 1.5 Gbits/s transmission.
16.2.2
Gen2i/3G Transmitter Specifications
This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i
or 3.0 Gbits/s transmission.
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i
or 3.0 Gbits/s transmission.
Table 56. Gen1i/1.5G Transmitter AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Channel speed
tCH_SPEED
1.5
Gbps
Unit interval
TUI
666.4333
666.667
670.2333
ps
Total jitter, data-data
5UI
USATA_TXTJ5UI
0.355
UIp-p
Total jitter, data-data
250 UI
USATA_TXTJ250UI
0.47
UIp-p
Deterministic jitter, data-data
5UI
USATA_TXDJ5UI
0.175
UIp-p
Deterministic jitter, data-data
250 UI
USATA_TXDJ250UI
0.22
UIp-p
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
Table 57. Gen 2i/3G Transmitter DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Tx differential output voltage
VSATA_TXDIFF
400
550
700
mVp-p
Tx differential pair impedance
ZSATA_TXDIFFIM
85
100
115
Ω
Note:
1. Terminated by 50
Ω load.
Table 58. Gen 2i/3G Transmitter AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Channel speed
tCH_SPEED
—3.0
Gbps
Unit interval
TUI
333.2
333.33
335.11
ps
Total jitter
fC3dB=fBAUD/10
USATA_TXTJfB/10
——
0.3
UIp-p
Total jitter
fC3dB =fBAUD/500
USATA_TXTJfB/500
0.37
UIp-p
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