參數(shù)資料
型號: MPC8378EVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 96/127頁
文件大小: 0K
描述: MPU PWRQUICC II 667MHZ 689TEPBGA
產(chǎn)品培訓模塊: MPC837x PowerQUICC II Pro Processors
視頻文件: Introduction to the MPC837x Family
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應商設備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
70
Freescale Semiconductor
This figure shows the SATA reference clock timing waveform.
Figure 45. SATA Reference Clock Timing Waveform
16.2
Transmitter (Tx) Output Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
16.2.1
Gen1i/1.5G Transmitter Specifications
This table provides the DC differential transmitter output DC characteristics for the SATA interface at
Gen1i or 1.5 Gbits/s transmission.
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
Cycle-to-cycle at
ref clock input
tCLK_CJ
100
ps
SD_REF_CLK/ SD_REF_CLK total
reference clock jitter, phase jitter
(peak-peak)
Peak-to-peak jitter
at ref clock input
tCLK_PJ
–50
+50
ps
Notes:
1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.
2. In a frequency band from 150 kHz to 15 MHz at BER of 10-12.
3. Total peak to peak Deterministic Jitter "DJ" should be less than or equal to 50 ps.
Table 55. Gen1i/1.5G Transmitter (Tx) DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Tx differential output voltage
VSATA_TXDIFF
400
500
600
mVp-p
Tx differential pair impedance
ZSATA_TXDIFFIM
85
100
115
Ω
Note:
1. Terminated by 50
Ω load.
Table 54. SATA Reference Clock Input Requirements (continued)
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Note
TH
TL
Ref_CLK
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