參數(shù)資料
型號: MPC8378EVRALG
廠商: Freescale Semiconductor
文件頁數(shù): 36/127頁
文件大?。?/td> 0K
描述: MPU PWRQUICC II 667MHZ 689TEPBGA
產(chǎn)品培訓(xùn)模塊: MPC837x PowerQUICC II Pro Processors
視頻文件: Introduction to the MPC837x Family
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
16
Freescale Semiconductor
5.2
RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications of the device.
Table 12 provides the PLL lock times.
6
DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip.
Note that DDR1 SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET to activate reset flow
32
tPCI_SYNC_IN
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
32
tCLKIN
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32
tPCI_SYNC_IN
HRESET assertion (output)
512
tPCI_SYNC_IN
HRESET negation to negation (output)
16
tPCI_SYNC_IN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
4—
tCLKIN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4—
tPCI_SYNC_IN
Input hold time for POR config signals with respect to negation of HRESET
0—
ns
Time for the device to turn off POR config signals with respect to the assertion of
HRESET
—4
ns
Time for the device to start driving functional output signals multiplexed with the
POR configuration signals with respect to the negation of HRESET
1—
tPCI_SYNC_IN
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.
Table 12. PLL Lock Times
Parameter
Min
Max
Unit
Note
PLL lock times
100
μs—
Note:
The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL
ratio. See Section 23, “Clocking,” for more information.
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MPC8378EVRANDA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
MPC8378EVRANFA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
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