參數資料
型號: MPC8378ECVRALGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數: 94/125頁
文件大小: 894K
代理商: MPC8378ECVRALGA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
70
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx UI.
NOTE
It is recommended that the recovered Tx UI be calculated using all edges in the 3500
consecutive UI interval with a fit algorithm using a minimization merit function (that is,
least squares and median deviation fits).
Figure 46. Minimum Transmitter Timing and Voltage Output Compliance Specifications
15.4.3
Differential Receiver (Rx) Input Specifications
The following table defines the specifications for the differential input at all receivers. The parameters are specified at the
component pins.
Table 58. Differential Receiver (Rx) Input Specifications
Parameter
Comments
Symbol
Min
Typical
Max
Units
Note
Unit interval
Each UPERX is 400 ps ± 300
ppm. UPERX does not account
for Spread Spectrum Clock
dictated variations.
UI
399.88
400
400.12
ps
1
Differential peak-to-peak
output voltage
VPEDPPRX = 2 |VRX-D+
VRX-D-|
VRX-DIFFp-p
0.175
1.200
V
2
Minimum receiver eye
width
The maximum interconnect
media and transmitter jitter that
can be tolerated by the receiver
can be derived as
TRX-MAX-JITTER = 1 –
UPEEWRX = 0.6 UI.
TRX-EYE
0.4
——UI
2, 3
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
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MPC8378ECVRAGFA 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
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