參數(shù)資料
型號： MPC8378ECVRALGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 89/125頁
文件大?。?/td> 894K
代理商： MPC8378ECVRALGA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
66
15
PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus.
15.1
DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK
15.2
AC Requirements for PCI Express SerDes Clocks
The following table lists the PCI Express SerDes clock AC requirements.
15.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
15.4
Physical Layer Specifications
Following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as
the specifications of the transport and data link layer, use the PCI Express Base Specification, Rev. 1.0a.
NOTE
The voltage levels of the transmitter and the receiver depend on the SerDes control registers
which should be programmed at the recommended values for PCI Express protocol (that is,
L1_nVDD = 1.0 V).
Table 56. SD_REF_CLK and SD_REF_CLK AC Requirements
Parameter
Symbol
Min
Typical
Max
Unit
Note
REFCLK cycle time
tREF
—10
—
ns
—
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles.
tREFCJ
—
100
ps
—
REFCLK phase jitter peak-to-peak. Deviation in edge location
with respect to mean edge location.
tREFPJ
–50
—
+50
ps
—
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
tCKCJ
—
100
ps
—
SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in
edge location with respect to mean edge location.
tCKPJ
–50
—
+50
ps
2, 3
Notes:
1. All options provide serial interface bit rate of 1.5 and 3.0 Gbps.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10-12.
3. Total peak-to-peak Deterministic Jitter “JD” should be less than or equal to 50 ps.
相關(guān)PDF資料
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