參數(shù)資料
型號(hào): MPC8378CVRANFA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁(yè)數(shù): 78/125頁(yè)
文件大?。?/td> 894K
代理商: MPC8378CVRANFA
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
56
tCLK_DELAY tDATA_DELAY < 10 + 0 2
tCLK_DELAY tDATA_DELAY < 8
11.3.2
High-Speed Input Path (Read)
This figure provides the data and command input timing diagram.
Figure 35. High-Speed Input Path
For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was driven by the SD card.
Since in this mode the SD card drives the data at the rising edge of the clock, a sufficient delay to the clock and the data must
exist to ensure it will not be sampled at the wrong internal clock falling edge. Note that the internal clock which is guaranteed
to be 50% duty cycle is used to sample the data, and therefore used in the equations.
11.3.2.1
High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and
SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tDATA_DELAY + tODLY + tSHSIVKH < 1.5 tSHSCK
Eqn. 15
tCLK_DELAY + tDATA_DELAY < 1.5 tSHSCK tODLY tSHSIVKH
Eqn. 16
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:
tCLK_DELAY + tDATA_DELAY < 30 14 5
tCLK_DELAY + tDATA_DELAY < 11
tCLK_DELAY
Output from the
SD CLK at
the Card Pin
SD Card Pins
tSHSIVKH
Driving
Edge
Sampling
Edge
tOH
tDATA_DELAY
tODLY
tSHSCK (Clock Cycle)
1/2 Cycle
tSHSIXKH
Right Edge
Wrong Edge
(MPC8378E Input Hold)
(MPC8378E Input Setup)
Input at the
MPC8378E Pins
SD CLK at the
MPC8378E Pin
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