參數(shù)資料
型號(hào): MPC8378CVRANFA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁(yè)數(shù): 22/125頁(yè)
文件大小: 894K
代理商: MPC8378CVRANFA
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
118
24
System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8378E.
24.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The AVDD level should always
be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent
filter circuits as illustrated in Figure 68, one to each of the five AVDD pins. By providing independent filters to each PLL, the
opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package,
without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Figure 68. PLL Power Supply Filter Circuit
24.2
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the device system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins
of the device. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device
using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be
used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD,
OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have
a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to
the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS
tantalum or Sanyo OSCON).
24.3
Connection Recommendations
To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate signal level. Unused
active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
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