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| 型號(hào)： | MPC8378CVRAJDA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁數(shù)： | 82/125頁 |
| 文件大?。?/td> | 894K |
| 代理商： | MPC8378CVRAJDA |
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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
6
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8378E. The device is
currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a
more complete reference. These are not purely I/O buffer design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
The following table provides the absolute maximum ratings.
Table 2. Absolute Maximum Ratings1
Characteristic
Symbol
Max Value
Unit
Note
Core supply voltage
VDD
–0.3 to 1.1
V
—
PLL supply voltage (e300 core, eLBC, and system)
AVDD
–0.3 to 1.1
V
—
DDR1 and DDR2 DRAM I/O voltage
GVDD
–0.3 to 2.75
–0.3 to 1.98
V—
Three-speed Ethernet I/O, MII management voltage
–0.3 to 3.63
V
—
PCI, DUART, system control and power management, I2C, and JTAG
I/O voltage
OVDD
–0.3 to 3.63
V
—
Local bus
LBVDD
–0.3 to 3.63
V
—
SerDes
–0.3 to 1.1
V
Input voltage
DDR DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
DDR DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
—
PCI, DUART, CLKIN, system control and power
management, I2C, and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
Local Bus
LBIN
–0.3 to (LBVDD + 0.3)
V
—
Storage temperature range
TSTG
–55 to 150
C—
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. (M,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
5. Overshoot/undershoot by OVIN on the PCI interface does not comply to the PCI Electrical Specification for 3.3-V operation,
as shown in Figure 2.
6. L[1,2]_nVDD includes SDAVDD_0, XCOREVDD, and XPADVDD power inputs.
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