參數(shù)資料
型號(hào): MPC8349VVAJF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù): 45/88頁(yè)
文件大小: 1014K
代理商: MPC8349VVAJF
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
5
Overview
— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
Universal serial bus (USB) multi-port host controller
— Can operate as a stand-alone USB host controller
– USB root hub with one or two downstream-facing ports
– Enhanced host controller interface (EHCI) compatible
– Complies with USB Specification Rev. 2.0
— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— Direct connection to a high-speed device without an external hub
— External PHY with serial and low-pin count (ULPI) interfaces
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Four chip selects support four external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin in core disable mode.
— Unique vector number for each interrupt source
Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded
hardware
DMA controller
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