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| 型號： | MPC8349VVAJF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672 |
| 封裝： | 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672 |
| 文件頁數(shù)： | 21/88頁 |
| 文件大?。?/td> | 1014K |
| 代理商： | MPC8349VVAJF |
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MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
28
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 13 shows the TBI receive AC timing diagram.
Figure 13. TBI Receive AC Timing Diagram
8.2.4
RGMII and RTBI AC Timing Specifications
Table 27 presents the RGMII and RTBI AC timing specifications.
Table 27. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
–0.5
—
0.5
ns
Data to clock input skew (at receiver)2
tSKRGT
1.0
—
2.8
ns
Clock cycle duration3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T4, 5
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX3, 5
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
0.75
ns
GTX_CLK125 reference clock period
tG12
6
—8.0
—
ns
GTX_CLK125 reference clock duty cycle
tG125H/tG125
47
—
53
%
Notes:
1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For
example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times
follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).
2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned.
5. Duty cycle reference is LVDD/2.
6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention.
PMA_RX_CLK1
RCG[9:0]
tTRX
tTRXH
tTRXR
tTRXF
tTRDVKH
PMA_RX_CLK0
tTRDXKH
tTRDVKH
tTRDXKH
tTRXH
Even RCG
Odd RCG
tSKTRX
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