參數(shù)資料
型號: MPC8347ZQADFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件頁數(shù): 49/98頁
文件大小: 1084K
代理商: MPC8347ZQADFB
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
53
Package and Pin Listings
Figure 37 and Figure 38 represent the AC timings from Table 54. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 37 shows the SPI timings in slave mode (external clock).
Figure 37. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 38 shows the SPI timings in master mode (internal clock).
Figure 38. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8347EA is available
in two packages—a tape ball grid array (TBGA) and a plastic ball grid array (PBGA). See Section 18.1,
18.1
Package Parameters for the MPC8347EA TBGA
The package parameters are provided in the following list. The package type is 35 mm
× 35 mm, 672 tape
ball grid array (TBGA).
Package outline
35 mm
× 35 mm
Interconnects
672
SPICLK (Input)
tNEIXKH
tNEIVKH
tNEKHOX
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
SPICLK (Output)
tNIIXKH
tNIKHOX
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH
相關(guān)PDF資料
PDF描述
MPC8347ZUAJFB 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672
MPC8347ECZQAGFB 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
MPC8347ECZUAJFB 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672
MPC8347EVVALFB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
MPC8347EZUAJDB 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672
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