參數(shù)資料
型號(hào): MPC8347VVAGFA
廠(chǎng)商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù): 93/108頁(yè)
文件大?。?/td> 1172K
代理商: MPC8347VVAGFA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
85
Clocking
Table 58 provides the operating frequencies for the MPC8347EA PBGA under recommended operating
conditions.
Table 57. Operating Frequencies for TBGA
Characteristic 1
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting
ccb_clk, MCLK,
LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating
frequency of the Security core and USB modules does not exceed the respective values listed in this table.
533 MHz
667 MHz
Unit
e300 core frequency (
core_clk)
266–533
266–667
MHz
Coherent system bus frequency
(
csb_clk)
100–266
100–333
MHz
DDR and DDR2 memory bus frequency
(MCLK) 2
2
The DDR data rate is 2x the DDR memory bus frequency.
100–200
MHz
Local bus frequency
(LCLK
n) 3
3
The local bus frequency is 1/2, 1/4, or 1/8 of the
lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the
ccb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
166
MHz
USB_DR, USB_MPH maximum internal operating frequency
133
166
MHz
Table 58. Operating Frequencies for PBGA
Characteristic 1
1
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting
ccb_clk, MCLK,
LCLK[0:2], and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating
frequency of the Security core and USB modules does not exceed the respective values listed in this table.
266 MHz
333 MHz
400 MHz
Unit
e300 core frequency (
core_clk)
200–266
200–333
200–400
MHz
Coherent system bus frequency (
csb_clk)
100–266
MHz
DDR memory bus frequency (MCLK) 2
2
The DDR data rate is 2x the DDR memory bus frequency.
100–133
MHz
Local bus frequency (LCLK
n) 3
3
The local bus frequency is 1/2, 1/4, or 1/8 of the
lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the
ccb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
MHz
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