參數(shù)資料
型號(hào)： MPC8347VVAGFA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝： 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù)： 90/108頁(yè)
文件大小： 1172K
代理商： MPC8347VVAGFA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 1
82
Freescale Semiconductor
Pinout Listings
LVDD1
U20, W25
Power for
Three Speed
Ethernet #1
and for
Ethernet
Management
Interface I/O
(2.5V, 3.3V)
LVDD1
LVDD2
V20, Y23
Power for
Three Speed
Ethernet #2
I/O (2.5V,
3.3V)
LVDD2
VDD
J11, J12, J15, K10, K11, K12, K13, K14,
K15, K16, K17, K18, K19, L10, L11, L18,
L19, M10, M19, N10, N19, P9, P10, P19,
R10, R19, R20, T10, T19, U10, U19, V10,
V11, V18, V19, W11, W12, W13, W14, W15,
W16, W17, W18
Power for
Core
(1.2 V)
VDD
OVDD
B27, D3, D11, D19, E15, E23, F5, F8, F11,
F14, F17, F20, G24, H23, H24, J6, J14, J17,
J18, K4, L9, L20, L23, L25, M6, M9, M20,
P5, P20, P23, R6, R9, R24, U23, V4, V6
PCI, 10/100
Ethernet, and
other
Standard
(3.3 V)
OVDD
MVREF1
AF19
I
DDR
Reference
Voltage
MVREF2
AE10
I
DDR
Reference
Voltage
No Connection
NC
V1, V2, V5
Notes:
1. This pin is an open-drain signal. A weak pull-up resistor (1 k
Ω) should be placed on this pin to OVDD
2. This pin is an open-drain signal. A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to OVDD.
3. During reset, this output is actively driven rather than three-stated.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.
6. .This pin must always be tied to GND
7. This pin must always be left not connected
8. Thermal sensitive resistor.
9. It is recommended that MDIC
0 be tied to GRD using an 18
Ω resistor and MDIC1 be tied to DDR power using an 18 Ω resistor.
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
相關(guān)PDF資料
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