參數(shù)資料
型號(hào): MPC8347EVVAGFA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA672
封裝: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-672
文件頁(yè)數(shù): 32/108頁(yè)
文件大小: 1172K
代理商: MPC8347EVVAGFA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
3
Overview
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE Std. 802.3, 802.3u, 820.3x, 802.3z, 802.3ac
— Ethernet physical interfaces:
– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
PCI interface
— Compatible with PCI specification revision 2.3
— Data bus width:
32-bit data PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— PCI host bridge capabilities
— PCI agent mode on PCI interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration supporting five masters on PCI
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
— Public key execution unit (PKEU) :
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
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