參數(shù)資料
型號: MPC8343EZQAGDX
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件頁數(shù): 43/92頁
文件大小: 987K
代理商: MPC8343EZQAGDX
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
48
Freescale Semiconductor
PCI
Table 35 provides the PCI AC timing specifications at 33 MHz.
Input setup to Clock
tPCIVKH
3.0
ns
2, 4
Input hold from Clock
tPCIXKH
0
ns
2, 4
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
6. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to User Manual, PCI chapter, description
of M66EN paragraph.
Table 35. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol 1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—11
ns
2
Output hold from Clock
tPCKHOX
2—
ns
2
Clock to output high impedance
tPCKHOZ
—14
ns
2, 3
Input setup to Clock
tPCIVKH
3.0
ns
2, 4
Input hold from Clock
tPCIXKH
0
ns
2, 4
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going
to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Table 34. PCI AC Timing Specifications at 66 MHz6 (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
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