參數(shù)資料
型號(hào)： MPC8343EZQAGDB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 6/80頁(yè)
文件大小： 0K
描述： IC MPU POWERQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
14
Freescale Semiconductor
RESET Initialization
5.2
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications of the MPC8343EA.
Table 11 lists the PLL and DLL lock times.
Table 10. RESET Initialization Timing Specifications
Parameter
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock applied to CLKIN when the
MPC8343EA is in PCI host mode
32
—
tCLKIN
2
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the MPC8343EA is in PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET/SRESET assertion (output)
512
—
tPCI_SYNC_IN
1
HRESET negation to SRESET negation (output)
16
—
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is
in PCI host mode
4—
tCLKIN
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is
in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of HRESET
0—
ns
—
Time for the MPC8343EA to turn off POR configuration signals with respect to the
assertion of HRESET
—4
ns
3
Time for the MPC8343EA to turn on POR configuration signals with respect to the
negation of HRESET
1—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs—
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”
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