參數(shù)資料
型號： MPC8343CVRAGD
廠商： Freescale Semiconductor
文件頁數(shù)： 26/80頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II PRO 620-PBGA
標準包裝： 36
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應商設備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
32
Freescale Semiconductor
Local Bus
10.2
Local Bus AC Electrical Specification
Table 34 and Table 35 describe the general timing parameters of the local bus interface of the
MPC8343EA.
Table 34. Local Bus General Timing Parameters—DLL On
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
—
ns
2
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
1.5
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
2.2
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
1.0
—
ns
3, 4
LUPWAIT Input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to LALE rise
tLBKHLR
—4.5
ns
—
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—4.5
ns
—
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—4.5
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—4.5
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKHOX1
1—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
1—
ns
3
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—3.8
ns
8
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)
for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one
(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output
(O) going invalid (X) or output hold time.
2. All timings are in reference to the rising edge of LSYNC_IN.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than
the load on the LAD output pins.
6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
load on the LAD output pins.
7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD
output pins.
8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
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