參數(shù)資料
型號(hào)： MPC8323ZQADDC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 3/82頁(yè)
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 266MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
11
RESET Initialization
4.2
AC Electrical Characteristics
The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the MPC8323E.
5
RESET Initialization
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8323E. Table 9 provides the reset initialization AC timing specifications for the reset
component(s).
CLKIN input current
0 V
≤ VIN ≤ OVDD
IIN
—±5
μA
PCI_SYNC_IN input current
0 V
≤ VIN ≤ 0.5 V or
OVDD – 0.5 V ≤ VIN ≤ OVDD
IIN
—±5
μA
PCI_SYNC_IN input current
0.5 V
≤ VIN ≤ OVDD – 0.5 V
IIN
—±50
μA
Table 8. CLKIN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
CLKIN/PCI_CLK frequency
fCLKIN
25
—
66.67
MHz
1
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
ns
—
CLKIN rise and fall time
tKH, tKL
0.6
0.8
4
ns
2
PCI_CLK rise and fall time
tPCH, tPCL
0.6
0.8
1.2
ns
2
CLKIN/PCI_CLK duty cycle
tKHK/tCLKIN
40
—
60
%
3
CLKIN/PCI_CLK jitter
—
±150
ps
4, 5
Notes:
1. Caution: The system, core, security, and QUICC Engine block must not exceed their respective maximum or minimum
operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset
flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock applied to CLKIN
when the MPC8323E is in PCI host mode
32
—
tCLKIN
2
Required assertion time of PORESET with stable clock applied to
PCI_SYNC_IN when the MPC8323E is in PCI agent mode
32
—
tPCI_SYNC_IN
1
Table 7. CLKIN DC Electrical Characteristics (continued)
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