參數(shù)資料
型號： MPC8323ZQADDC
廠商： Freescale Semiconductor
文件頁數(shù)： 17/82頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標準包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 266MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
24
Freescale Semiconductor
Ethernet and MII Management
Figure 11 provides the AC test load.
Figure 11. AC Test Load
Figure 12 shows the RMII receive AC timing diagram.
Figure 12. RMII Receive AC Timing Diagram
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
REF_CLK clock fall time VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock
reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to
the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
Table 26. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
REF_CLK
RXD[1:0]
tRMRDXKH
tRMX
tRMXH
tRMXR
tRMXF
CRS_DV
RX_ER
tRMRDVKH
Valid Data
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