參數(shù)資料
型號： MPC8323EZQADDC
廠商： Freescale Semiconductor
文件頁數(shù)： 78/82頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 266MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
8
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.1.4
Input Capacitance Specification
Table 4 describes the input capacitance for the CLKIN pin in the MPC8323E.
2.2
Power Sequencing
The device does not require the core supply voltage (VDD) and IO supply voltages (GVDD and OVDD) to
be applied in any particular order. Note that during power ramp-up, before the power supplies are stable
and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input
and output pins are actively driven and cause contention and excessive current. In order to avoid actively
driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O
voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case
where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before
the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are
stable, wait for a minimum of 32 clock cycles before negating PORESET.
Note that there is no specific power down sequence requirement for the device. I/O voltage supplies
(GVDD and OVDD) do not have any ordering requirements with respect to one another.
Table 3. Output Drive Capability
Driver Type
Output Impedance
(
Ω)
Supply
Voltage
Local bus interface utilities signals
42
OVDD = 3.3 V
PCI signals
25
DDR1 signal
18
GVDD = 2.5 V
DDR2 signal
18
GVDD = 1.8 V
DUART, system control, I2C, SPI, JTAG
42
OVDD = 3.3 V
GPIO signals
42
OVDD = 3.3 V
Table 4. Input Capacitance Specification
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input capacitance for all pins except CLKIN
CI
68
pF
—
Input capacitance for CLKIN
CICLKIN
10
—
pF
1
Note:
1. The external clock generator should be able to drive 10 pF.
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MPC8323EZQADDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
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MPC8323EZQAFDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
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