
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
64
Freescale Semiconductor
Clocking
22 Clocking
Figure 43 shows the internal distribution of clocks within the MPC8323E.
Figure 43. MPC8323E Clock Subsystem
The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode, respectively.
Core PLL
System
LBC
LCLK[0:1]
core_clk
e300c2 core
csb_clk to rest
CLKIN
csb_clk
Local Bus
PCI_CLK_OUT[0:2]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the device
lbc_clk
PCI Clock
PCI_SYNC_IN
Memory
Device
/n
to local bus
Clock
Divider (
÷2)
3
MEMC_MCK
DDR
ddr_clk
DDR
Memory
Device
PLL
to DDR
memory
controller
Clock
CFG_CLKIN_DIV
/2
Divider
1
0
QUICC
PLL
Engine
ce_clk to QUICC
Engine block
MPC8323E
Crystal
CLKIN