• 參數(shù)資料
    型號: MPC8323CZQAFDCA
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 333 MHz, RISC PROCESSOR, PBGA516
    封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516
    文件頁數(shù): 40/82頁
    文件大小: 1134K
    代理商: MPC8323CZQAFDCA
    MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
    Freescale Semiconductor
    45
    HDLC, BISYNC, Transparent, and Synchronous UART
    19 HDLC, BISYNC, Transparent, and Synchronous
    UART
    This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
    BISYNC, transparent, and synchronous UART of the MPC8323E.
    19.1
    HDLC, BISYNC, Transparent, and Synchronous UART DC
    Electrical Characteristics
    Table 50 provides the DC electrical characteristics for the MPC8323E HDLC, BISYNC, transparent, and
    synchronous UART protocols.
    19.2
    HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
    Specifications
    Table 51 provides the input and output AC timing specifications for HDLC, BISYNC, and transparent
    UART protocols.
    Table 50. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
    Characteristic
    Symbol
    Condition
    Min
    Max
    Unit
    Output high voltage
    VOH
    IOH = –2.0 mA
    2.4
    V
    Output low voltage
    VOL
    IOL = 3.2 mA
    0.5
    V
    Input high voltage
    VIH
    —2.0
    OVDD +0.3
    V
    Input low voltage
    VIL
    –0.3
    0.8
    V
    Input current
    IIN
    0 V
    ≤ VIN ≤ OVDD
    ±5
    μA
    Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications1
    Characteristic
    Symbol2
    Min
    Max
    Unit
    Outputs—Internal clock delay
    tHIKHOV
    05.5
    ns
    Outputs—External clock delay
    tHEKHOV
    110
    ns
    Outputs—Internal clock high impedance
    tHIKHOX
    05.5
    ns
    Outputs—External clock high impedance
    tHEKHOX
    18
    ns
    Inputs—Internal clock input setup time
    tHIIVKH
    6—
    ns
    Inputs—External clock input setup time
    tHEIVKH
    4—
    ns
    Inputs—Internal clock input hold time
    tHIIXKH
    0—
    ns
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