參數(shù)資料
型號(hào)： MPC8315VRAFDA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, MICROPROCESSOR, PBGA620
封裝： 29 X 29 MM, 2.23 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-620
文件頁(yè)數(shù)： 57/112頁(yè)
文件大?。?/td> 1283K
代理商： MPC8315VRAFDA
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
49
I
2C
13.2
I2C AC Electrical Specifications
Table 48 provides the AC timing parameters for the I2C interface.
Input current (0 V
≤VIN ≤ NVDD)
IIN
—± 5
μA4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. See the
MPC8315E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter
used.
4. I/O pins obstruct the SDA and SCL lines if NVDD is switched off.
Table 48. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 47)
Parameter
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0400
kHz
Low period of the SCL clock
tI2CL
1.3
—
μs
High period of the SCL clock
tI2CH
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
Hold time (repeated) START condition (after this period, the first clock pulse is
generated)
tI2SXKL
0.6
—
μs
Data setup time
tI2DVKH
100
—
ns
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0 2
—
0.9 3
μs
Fall time of both SDA and SCL signals
tI2CF
4
—
300
ns
Setup time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including hysteresis)
VNL
0.1
× NVDD
—
V
Table 47. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with NVDD of 3.3 V ± 300 mv
Parameter
Symbol
Min
Max
Unit
Notes
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