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參數(shù)資料
| 型號： | MPC8314EVRAGDA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 98/101頁 |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC II PRO 620-PBGA |
| 標準包裝： | 36 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 400MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 620-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 620-PBGA（29x29） |
| 包裝： | 托盤 |
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MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
96
Freescale Semiconductor
System Design Information
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias. Note that the RC filter results in
lower voltage level on AVDD. This does not imply that the DC specification can be relaxed.
This figure shows the PLL power supply filter circuit.
Figure 61. PLL Power Supply Filter Circuit
25.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8314E system, and the
MPC8314E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pins
of the device. These decoupling capacitors should receive their power from separate VDD, NVDD,
GVDD, LVDD, and GND power planes in the PCB, utilizing thick and short traces to minimize
inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others
may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, NVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo
OSCON).
25.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to NVDD, GVDD, or LVDD as required. Unused active
high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
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