參數(shù)資料
型號(hào)： MPC8314EVRAGDA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 15/101頁(yè)
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC83xx
處理器類(lèi)型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤(pán)
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
20
Freescale Semiconductor
DDR and DDR2 SDRAM
MCS[n] output hold with respect to MCK
266 MHz
200 MHz
tDDKHCX
3.15
4.20
—
ns
3
MCK to MDQS Skew
tDDKHMH
–0.6
0.6
ns
4
MDQ//MDM output setup with respect to MDQS
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
900
1000
—
ps
5
MDQ//MDM output hold with respect to MDQS
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
1100
1200
—
ps
5
MDQS preamble start
tDDKHMP
–0.5
t
MCK – 0.6
–0.5
t
MCK + 0.6
ns
6
MDQS epilogue end
tDDKHME
–0.6
0.6
ns
6
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust
in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the
same adjustment value. See the MPC8315E PowerQUICC II Pro Integrated Host Processor Family Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (),
or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions
Parameter
Symbol 1
Min
Max
Unit
Note
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MPC8314VRAFDA 功能描述:微處理器 - MPU NON-ENCRYPT RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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MPC8315 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8315E PowerQUICC II Pro Processor Hardware Specifications
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