參數(shù)資料
型號(hào): MPC8306SCVMADDCA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369
封裝: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件頁數(shù): 55/71頁
文件大?。?/td> 452K
代理商: MPC8306SCVMADDCA
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
59
Clocking
20.3
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 51 shows the encodings for RCWL[COREPLL]. COREPLL values not listed
in Table 51 should be considered reserved.
NOTE
Core VCO frequency = core frequency
VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO
frequency is in the range of 400–800 MHz.
Table 51. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider
0-1
2-5
6
nn
0000
n
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
00
0001
0
1:1
2
01
0001
0
1:1
4
10
0001
0
1:1
8
11
0001
0
1:1
8
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
10
0001
1
1.5:1
8
11
0001
1
1.5:1
8
00
0010
0
2:1
2
01
0010
0
2:1
4
10
0010
0
2:1
8
11
0010
0
2:1
8
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
10
0010
1
2.5:1
8
11
0010
1
2.5:1
8
00
0011
0
3:1
2
01
0011
0
3:1
4
10
0011
0
3:1
8
11
0011
0
3:1
8
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