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| 型號： | MPC8280ZUUPEA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 14/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 450MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應(yīng)商設(shè)備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
| 其它名稱： | MPC8280ZUUPE MPC8280ZUUPE-ND |
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MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
Freescale Semiconductor
21
AC Electrical Characteristics
NOTE: Conditions
The following conditions must be met in order to operate the MPC8272
family devices with 133 MHz bus: single PowerQUICC II Bus mode must
be used (no external master, BCR[EBM] = 0); data bus must be in Pipeline
mode (BRx[DR] = 1); internal arbiter and memory controller must be used.
For expected load of above 40 pF, it is recommended that data and address
buses be configured to low (25
Ω) impedance (SIUMCR[HLBE0] = 1,
SIUMCR[HLBE1] = 1).
This table lists SIU output characteristics.
Table 11. AC Characteristics for SIU Inputs1
1 Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
Spec Number
Characteristic
Value (ns)
Setup
Hold
Setup
Hold
66
MHz
83
MHz
100
MHz
133
MHz
66
MHz
83
MHz
100
MHz
133
MHz
sp11
sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/TEA
6
5
3.5
N/A
0.5
N/A
sp12
sp10 Data bus in normal mode
5
4
3.5
N/A
0.5
N/A
sp13
sp10 Data bus in pipeline mode (without ECC and
PARITY)
N/A
4
2.5
1.5
N/A
0.5
sp15
sp10 All other pins
5
4
3.5
N/A
0.5
N/A
Table 12. AC Characteristics for SIU Outputs1
1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
Spec Number
Characteristic
Value (ns)
Max
Min
Maximum Delay
Minimum Delay
66
MHz
83
MHz
100
MHz
133
MHz
66
MHz
83
MHz
100
MHz
133
MHz
sp31
sp30
PSDVAL/TEA/TA
7
6
5.5
N/A
1
N/A
sp32
sp30
ADD/ADD_atr./BADDR/CI/GBL/WT
8
6.5
5.5
4.52
2 Value is for ADD only; other sp32/sp30 signals are not applicable.
11
1
1 2
sp33
sp30
Data bus3
3 To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.
6.5
5.5
4.5
0.8
1
sp34
sp30
Memory controller signals/ALE
6
5.5
4.5
1
sp35
sp30
All other signals
6
5.5
N/A
1
N/A
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