參數(shù)資料
型號(hào)： MPC8272ZQPIEX
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAL-1, BGA-516
文件頁(yè)數(shù)： 18/60頁(yè)
文件大?。?/td> 746K
代理商： MPC8272ZQPIEX
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 2
Freescale Semiconductor
25
Clock Configuration Modes
7
Clock Configuration Modes
As shown in Table 15, the clocking mode is set according to two sources:
PCI_CFG[0]— An input signal. Also defined as “PCI_HOST_EN.” Refer to the Chapter 6,
“External Signals,” and Chapter 9, “PCI Bridge,” in the MPC8272 PowerQUICC II Family
Reference Manual.
PCI_MODCK—Bit 27 in the Hard Reset Configuration Word. Refer to Chapter 5, “Reset,” in the
MPC8272 PowerQUICC II Family Reference Manual.
Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits
during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from
JTAG external clock to output high impedance
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
1
10
ns
5, 6
1 All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load.
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2 The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
(V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K)
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4 Non-JTAG signal input timing with respect to t
TCLK.
5 Non-JTAG signal output timing with respect to t
TCLK.
6 Guaranteed by design.
7 Guaranteed by design and device characterization.
Table 15. MPC8272 Clocking Modes
Pins
Clocking Mode
PCI Clock Frequency Range (MHz)
Reference
PCI_CFG[0] 1
1
PCI_HOST_EN
PCI_MODCK 2
2
Determines PCI clock frequency range.
0
PCI host
50–66
0
1
25–50
1
0
PCI agent
50–66
1
25–50
Table 14. JTAG Timings1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
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