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參數(shù)資料
| 型號(hào)： | MPC826XAZUSPUX |
| 廠商： | Motorola, Inc. |
| 英文描述： | MPC826xA (HiP4) Family Hardware Specifications |
| 中文描述： | MPC826xA（HiP4）家庭硬件規(guī)格 |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 315K |
| 代理商： | MPC826XAZUSPUX |
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MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
Figure 9 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 9. Parity Mode Diagram
Figure 10 shows signal behavior in MEMC mode.
Figure 10. MEMC Mode Diagram
NOTE
Generally, all MPC826xA bus and system output signals are driven from
the rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
Table 13. Tick Spacing for Memory Controller Signals
PLL Clock Ratio
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
3/10 CLKin
1/2 CLKin
8/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
11/14 CLKin
CLKin
DATA bus, ECC, and PARITY mode input signals
DP mode input signal
DP mode output signal
sp13
sp10
sp14
sp10
sp33b/sp30
CLKin
V_CLK
Memory controller signals
sp34/sp30
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