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| 型號： | MPC8260ACZUMIBB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, TBGA-480 |
| 文件頁數(shù)： | 12/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | MPC8260ACZUMIBB |
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MPC8260 (HiP3) Hardware Specications
MOTOROLA
Features
Figure 1 shows the block diagram for the MPC8260.
Figure 1. MPC8260 Block Diagram
1.1
Features
The major features of the MPC8260 are as follows:
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the
MPC8255)
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
16 Kbytes
G2 Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
24 Kbytes
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
2 Virtual
IDMAs
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
Local Bus
32 bits, up to 66 MHz
MCC11
MCC2
FCC1
FCC2
FCC31
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
Serial Interface
3 MII
2 UTOPIA
Ports
Ports3
60x Bus
Dual-Port RAM
Interrupt
Controller
Time Slot Assigner
8 TDM Ports2
Non-Multiplexed
I/O
60x-to-Local
Bus Interface Unit
Notes:
1 Not on MPC8255
2 4 on the MPC8255
3 2 on the MPC8255
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