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參數(shù)資料
| 型號： | MPC8250AZUPIBC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37 X 37 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件頁數(shù)： | 15/73頁 |
| 文件大?。?/td> | 885K |
| 代理商： | MPC8250AZUPIBC |
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22
MPC8250 Hardware Specications
MOTOROLA
Clock Conguration Modes
1.3.2
PCI Mode
The PCI mode is selected according to three input pins, as shown in Table 12. In addition, note the
following:
NOTE: PCI_MODCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.
NOTE: Tval (Output Hold)
The minimum Tval = 2 when PCI_MODCK = 1, and the minimum
Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock
congurations that t this condition to achieve PCI-compliant AC timing.
NOTE
Clock congurations change only after POR is asserted.
1.3.2.1
PCI Host Mode
The frequencies listed are for the purpose of illustration only. Users must select a mode and input bus
frequency so that the resulting conguration does not exceed the frequency rating of the user’s device.
0111_111
66 MHz
3.5
233 MHz
2
133 MHz
1000_000
66 MHz
3.5
233 MHz
2.5
166 MHz
1000_001
66 MHz
3.5
233 MHz
3
200 MHz
1000_010
66 MHz
3.5
233 MHz
3.5
233 MHz
1000_011
66 MHz
3.5
233 MHz
4
266 MHz
1000_100
66 MHz
3.5
233 MHz
4.5
300 MHz
1 Because of speed dependencies, not all of the possible congurations in Table 14 are applicable.
2 The user should choose the input clock frequency and the multiplication factors such that the frequency of the
CPU is equal to or greater than 133 MHz (150 MHz for extended temperature parts) and the CPM ranges
between 66–233 MHz.
3 Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting conguration does not exceed the frequency rating of the user’s part.
Table 14. Clock Configuration Modes1 (Continued)
MODCK_H–MODCK[1–3]
Input Clock
Frequency2,3
CPM Multiplication
Factor2
CPM
Frequency2
Core Multiplication
Factor2
Core
Frequency2
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