參數(shù)資料
型號: MPC8245TVV300D
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352
文件頁數(shù): 22/68頁
文件大?。?/td> 1143K
代理商: MPC8245TVV300D
MPC8245 Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
29
Electrical and Thermal Characteristics
Figure 18. I2C Timing Diagram III
Figure 19. I2C Timing Diagram IV (Qualified Signal)
4.3.5
PIC Serial Interrupt Mode AC Timing Specifications
Table 15 provides the PIC serial interrupt mode AC timing specifications for the MPC8245 at
recommended operating conditions (see Table 2) with GVDD = 3.3 V ± 5% and LVDD = 3.3 V ± 0.3 V.
Table 15. PIC Serial Interrupt Mode AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
S_CLK frequency
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
1
2
S_CLK duty cycle
40
60
%
3
S_CLK output valid time
6
ns
4
Output hold time
0
ns
5S_FRAME, S_RST output valid time
1 sys_logic_clk period + 6
ns
2
6
S_INT input setup time to S_CLK
1 sys_logic_clk period + 2
ns
2
7
S_INT inputs invalid (hold time) to S_CLK
0
ns
2
Notes:
1. See the MPC8245 Integrated Processor Reference Manual for a description of the PIC interrupt control register (ICR) and
S_CLK frequency programming.
2. S_RST, S_FRAME, and S_INT shown in Figure 20 and Figure 21, depict timing relationships to sys_logic_clk and S_CLK
and do not describe functional relationships between S_RST, S_FRAME, and S_INT. The MPC8245 Integrated Processor
Reference Manual describes the functional relationships between these signals.
3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is
implemented and the DLL is locked. See the MPC8245 Integrated Processor Reference Manual for a complete clocking
description.
Input Data Valid
DFFSR Filter Clock
SDA
7
Note: DFFSR filter clock is the SDRAM_CLK clock times DFFSR value.
SCL/SDArealtime
VM
SCL/SDAqualified
VM
Delay
Note: The delay is the local memory clock times DFFSR times two plus one local memory clock.
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MPC8245TVV350D 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
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