參數(shù)資料
型號(hào)： MPC8245LZU300X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁(yè)數(shù)： 4/60頁(yè)
文件大?。?/td> 620K
代理商： MPC8245LZU300X
12
MPC8245 Integrated Processor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.1.5 Power Characteristics
Table 5 provides preliminary, estimated power consumption data for the MPC8245.
Table 5. Preliminary Power Consumption
Mode
PCI Bus Clock / Memory Bus Clock
CPU Clock Frequency (MHz)
Units
Notes
66/
266
66/
133/
266
66/
300
66/
100/
300
33/
83/
333
66/
133/
333
66/
100/
350
Typical
1.5
(1.2)
1.7
(1.3)
1.6
(1.3)
1.7
(1.4)
1.8
2.0
1.9
W
1, 5
Max - FP
1.9
(1.5)
2.1
(1.7)
2.0
(1.6)
2.1
(1.7)
2.2
2.4
W
1, 2
Max - INT
1.6
(1.3)
1.8
(1.5)
1.7
(1.4)
1.9
(1.5)
1.9
2.1
W
1, 3
Doze
1.0
(0.8)
1.3
(1.0)
1.1
(0.9)
1.3
(1.0)
1.3
1.5
1.4
W
1, 4, 6
Nap
0.3
(0.3)
0.5
(0.5)
0.4
(0.3)
0.5
(0.4)
0.4
0.6
0.5
W
1, 4, 6
Sleep
0.4
(0.3)
0.2
(0.2)
0.4
(0.3)
0.4
(0.3)
0.2
0.4
W
1, 4, 6
I/O Power Supplies10
Mode
Minimum
Maximum
Units
Notes
Typ-OVdd
200
500
mW
7,8
Typ-GVdd
300
600
mW
7,9
Notes:
1
The values include Vdd, AVdd, and AVdd2 but do not include I/O Supply Power, see Section 1.7.3, “Power
Supply Sizing,” for information on OVdd and GVdd supply power. Values shown in parenthesis () indicate
power consumption at Vdd/AVdd/AVdd2 = 1.8 V.
2
Maximum - FP power is measured at Vdd = 2.1 V with dynamic power management enabled while running
an entirely cache-resident, looping, oating point multiplication instruction.
3
Maximum - INT power is measured at Vdd = 2.1 V with dynamic power management enabled while running
entirely cache-resident, looping, integer instructions.
4
Power saving mode maximums are measured at Vdd = 2.1 V while the device is in doze, nap, or sleep mode.
5
Typical power is measured at Vdd = AVdd = 2.0V, OVdd = 3.3 V where a nominal FP value, a nominal INT
value, and a value where there is a continuous ush of cache lines with alternating ones and zeroes on 64
bit boundaries to local memory are averaged.
6
Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7
The typical minimum I/O power values were results of the MPC8245 performing cache resident integer oper-
ations at the slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.
8
The typical maximum OVdd value resulted from the MPC8245 operating at the fastest frequency combina-
tion of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous ushes of cache lines with alternating
ones and zeroes to PCI memory.
9
The typical maximum GVdd value resulted from the MPC8245 operating at the fastest frequency combina-
tion of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous ushes of cache lines with alternating
ones and zeroes on 64 bit boundaries to local memory.
10 Power consumption of PLL supply pins (AVdd and AVdd2) < 15 mW. Guaranteed by design and is not
tested.
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